TLE6361G_05 Datasheet, PDF (13/57 Pages) Infineon Technologies AG – Multi-Voltage Processor Power Supply

TLE 6361 G
Q_LDO1 has decreased below 3.3V (max.) the default settings are valid, means the
64ms delay time. If the voltage on Q_LDO1 during sleep or power off mode was kept
above 3.3V the delay time set by the last SPI command is valid.
V_{FB/L_IN}
V_{Q_LDOx}
t_rr
V_Rx
t_RES
t_RES
< t_rr
t_RES
t
V_{RTH,Q_LDOx}
t
t_RES
t
thermal
under
over
shutdown
voltage
load
Figure 5 Undervoltage reset timing
2.7 RAM good flag
A RAM good flag will be set within the SPI status word when the Q_LDO1 voltage drops
below 2.3V. A second one will be set if Q_LDO2 drops below typical 1.4V. Both RAM
good flags can be read after power up to determine if a cold or warm start needs to be
processed. Both RAM good flags will be reset after each SPI cycle.
2.8 ERR Pin
An hardware error pin indicates any fault conditions on the chip. It should be connected
to an interrupt input of the microcontroller. A low signal indicates an error condition. The
microcontroller can read the root cause of the error by reading the SPI register.
2.9 Window Watchdog
The on board window watchdog for supervision of the µC works in combination with the
SPI. The window watchdog logic is triggered when CS is low and Bit WD-Trig in the SPI
command word is set to “1”. The watchdog trigger is recognized with the low to high
transition of the CS signal. To allow reading the SPI at any time without getting a reset
due to misinterpretation the WD-Trig bit has to be set to “0” to avoid false trigger
conditions. To disable the window watchdog the WD-OFF bits need to be set to “010”.
Data Sheet, Rev. 2.0
13
2005-03-01