ICE2HS01G Datasheet, PDF (17/29 Pages) Infineon Technologies AG – High Performance Resonant Mode Controller

High Performance Resonant Mode Controller
ICE2HS01G
Functional description
IC delay pin is regulated at a constant voltage, the current, depending on external resistor only, is used to calculate this turn-
off delay. The turn-off delay is 330ns when R_delay is 51kΩ. In addition, the relationship of turn-off delay time and delay
resistance is shown in Figure 15.
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
10
20
30
40
50
60
70
80
90
100
110
Rde lay(k Ω)
Figure 15 Relationship between Rdelay and Tdelay
3.7.4
SR protections
As the SR control in ICE2HS01G is realized with indirect method, there are some cases that the SR can not work properly.
In this cases, the SR gate drive will be disabled. Once the condition is over, IC will restart the SR with SRSoftstart.
During softstart, the SR is disabled. When the softstart pin voltage is higher than 1.9V for 20ms, SR will be enabled with
SRSoftstart.
When LOAD pin voltage is lower than 0.2V, IC will disable the SR immediately. If LOAD pin voltage is higher than 0.7V,
IC will resume SR with SRSoftstart.
During over-current protection phase, if the softstart pin voltage is lower than 1.8V, SR will be disabled. The SR will resume
with softstart 10ms after SS pin voltage is higher than 1.9V again.
In over-current protection, if the CS pin voltage is higher than 0.9V, SR is disabled. SR will be enabled with SRSoftstart after
CS pin voltage is lower than 0.6V.
All the above four conditions are built inside the IC. If IC detects such a condition, IC will disable SR and pull down the
voltage on SRD pin to zero.
When the CS voltage suddenly drops from 0.55V to below 0.30V within 1ms, the SR gate is turned off for 1ms, after 1ms,
SR operation is enabled again with SRsoftstart.
An addition option is also provided. If some fault conditions are not reflected on the four conditions mentioned above but can
be detected outside with other measures, the SR can also be disabled and enabled with softstart from outside. This is
implemented on SRD pin as well. The internal SRD reference voltage has limited current source capability. If a transistor
Q_SRD is connected as shown in typical application circuit, the voltage on SRD pin can be pulled to zero if this transistor is
turned on, which will stop the SR. If the SRD voltage is released and increases above 1.75V, SR is enabled with softstart.
3.7.5
SR softstart
The SR operaton is enabled after the output voltage has been built up. However, as the SR MOSFET drain-source voltage
drop is much lower than the forward voltage drop of the body diodes or the schottky diodes, the output power of the converter
will increase a lot if the SR MOSFETs are started with full duty. In ICE2HS01G, SR operation will start with small duty. The
SR MOSFET will start with its own softstart, the duty cycle for first pulse is around one-tenth of its normal duty, which will
be kept same for 16 consective switching cycles. Then, the duty is increased gradually step by step to the full duty. Total 7
steps are built for the softstart and each step includes 16 switching cycles. Therefore, after 128 switching cycles, the SR duty
will reach its normal value.
Version 2.0
17
11 May 2010