ICE2HS01G Datasheet, PDF (15/29 Pages) Infineon Technologies AG – High Performance Resonant Mode Controller

High Performance Resonant Mode Controller
ICE2HS01G
Functional description
The Missing Cycle mode can be disabled by pulling down Vmc pin to ground. In this case, even very low voltage on CS pin
will let the IC works in normal mode. It is recommended to use a 10k resistor for pulling down purpose.
The Burst Mode (BM) operation in ICE2HS01G is implemented with LOAD pin voltage. If the voltage on LOAD pin is lower
than 0.1V, all the gate drives will be pulled low after the next high side switch cycle is finished. If the LOAD pin voltage
increases higher than 0.15V, IC will resume switch. Every time IC resumes switch from burst mode, the first pulse will be
high gate with reduced duty cycle.
In certain conditions, Burst Mode opeation is not wanted and can be disabled. The method will be described in Section 3.10.
3.7 Synchronous Rectification
Synchronous Rectification (SR) in a half-bridge LLC resonant converter is the key to achieve very high efficiency, and this
is the major benefits from the patent pending method integrated in ICE2HS01G. The control of Synchronous Rectification in
ICE2HS01G have four main parts: On time control, turn-on delay, turn-off delay and protections, with the block diagram
shown in Figure 12.
Figure 12 Synchronous rectification control block diagram
3.7.1
SR On time control
The oscillator of SR control, with divide-by-two function, determines the on time of both SR gates. It uses regulated current
to charge the capacitor, while the current is proportional to current flowing out of SRD pin and the capacitor is fixed inside
the IC. The SRD pin is regulated to 2V. On time of SR gates can then be programmed by regulating the equivalent resistance
connected to SRD pin.
In typical conditions, a 5µs SR on time is set when the equivalent resistance from SRD pin to ground is 62kΩ. The typical
relation between SRD resistance and the corresponding SR on time can be found in Figure 13. The internal circuit of SRD
pin is designed with certain limit of maximum current flowing out. The minimum resistor, or equivalent resistance to SRD
pin, can not be less than 15kΩ.
A simple constant on time control does not provide the best performance of LLC HB converter. In fact, the actual resonant
period of secondary current reduces when the output load decreases or input voltage increases. The primary winding current
can reflects this change. Certain current sense circuit can be used to get such information and input to ICE2HS01G on CS
pin. In ICE2HS01G, a function called current level (CL) pin is implemented. During heavy load and low input voltage, the
CL pin voltage is clamped at same voltage of SRD pin. Therefore, the SR on time in such conditions is determined by R_SRD
only. In case of light load, with low CS voltage, the CL pin voltage is reduced and therefore the actual SR on time is reduced
Version 2.0
15
11 May 2010