TLE7469_08 Datasheet, PDF (16/21 Pages) Infineon Technologies AG – Dual Low Drop Voltage Regulator Ultra low quiescent current consumption < 55 μA

TLE 7469
V_I
t
V_Q1
V_RT1
t
V_Q2
V_RT2
T_RR
T_RR
t
V_RO
T_RD
T_RD
T_RD
V
ROH
V_ROL
Figure 5 Reset Function and Timing Diagram
t
AET03532.VSD
Watchdog Operation
The watchdog uses a fraction of the charge pump oscillator’s clock signal as timebase.
Connecting the DT pin to Q1 or to Q2 the watchdog timebase can be adjusted. The
watchdog can be turned off by a low level (V_DT ≤ 0.8 V) applied to the DT pin. The timing
values used in this text refer to typ. values with DT connected to Q1 (fast timing).
Figure 6 shows the state diagram of the window watchdog (WWD). After power-on, the
reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay
time T_RD of typ. 8 ms. With the LOW to HIGH transition of the signal at RO the device
starts the ignore window time t_CW (32 ms). During this window the signal at the WDI pin
is ignored. Next the WWD starts the open window. When a valid trigger signal is detected
during the open window a closed window is initialized immediately. A trigger signal within
Data Sheet
16
Rev. 1.6, 2008-01-22