TLE7469_08 Datasheet, PDF (15/21 Pages) Infineon Technologies AG – Dual Low Drop Voltage Regulator Ultra low quiescent current consumption < 55 μA

TLE 7469
Circuit Description
Power On Reset
In order to avoid any system failure, a sequence of several conditions has to be passed.
When the level of V_Q2 reaches the reset threshold V_RT, the signal at RO remains LOW
for the Power-up reset delay time T_RD. Then a second comparator checks whether
V_Q1 ≥ V_RT1 and only if this test is passed the reset output is switched to HIGH. The Reset
output is only released (set to High level) if both output voltages have passed their
specific reset threshold V_RT1/2. The reset function and timing is illustrated in Figure 5.
The reset reaction time T_RR avoids wrong triggering caused by short “glitches” on the
V_Q2-line. For power-fail, in case of V_Q2 or V_Q1 power down (V_Q2 < V_RT2 or V_Q1 < V_RT1 for
t > T_RR) a logic LOW signal is generated at the pin RO to reset an external
microcontroller.
Data Sheet
15
Rev. 1.6, 2008-01-22