TLE6288R_10 Datasheet, PDF (16/32 Pages) Infineon Technologies AG – Smart 6 Channel Peak & Hold Switch

TLE6288R
SPI
edge (if CLKProg = L; rising edge if CLKProg = H) of serial clock. It is essential that the SCLK pin is in a logic high
state (if CLKProg = L; low state if CLKProg = H) whenever chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit (MSB) first. SI information is read
in on the rising edge of SCLK (if CLKProg = L; falling edge if CLKProg = H). Input data is latched in the SPI shift
register and then transferred to the internal registers of the logic.
The input data consists of 16 bits, made up of 4 control bits and 12 data bits. The control word is used to program
the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 5.5).
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit (MSB) first. SO
is in a high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO
pin following the falling edge of SCLK (if CLKProg = L; rising edge if CLKProg = H).
5.2
Electrical Characteristics: SPI Timing
Electrical Characteristics: SPI Timing
V_CC = 4.5 V to 5.5 V, T_j = -40 ⋅C to +150 ⋅C, V_B = 6 V to 16 V, Reset = H, V_DO = V_CC, all voltages with respect to
ground, positive current flowing into pin (unless otherwise specified)
Pos. Parameter
Symbol
Limit Values
Unit Pin/
Conditions
Min. Typ. Max.
Comment
5.2.1 Serial Clock Frequency
f_SCLK
DC
–
5
MHz –
–
(depending on SO load)
5.2.2 Serial Clock Period (1/f_SCLK) t_p(SCLK) 200
–
–
ns –
5.2.3 Serial Clock High Time
t_SCLKH
50
–
–
ns –
5.2.4 Serial Clock Low Time
t_SCLKL
50
–
–
ns –
5.2.5 Enable Lead Time
t_leadL
200 –
–
ns –
(falling edge of CS to falling
edge of SCLK)
–
–
–
CLKProg = L
Enable Lead Time
t_leadH
200 –
–
ns –
(falling edge of CS to rising
edge of SCLK)
CLKProg = H
5.2.6 Enable Lag Time (rising edge t_lagL
200 –
–
ns –
of SCLK to rising edge of CS)
CLKProg = L
Enable Lag Time (falling edge t_lagH
200 –
–
ns –
of SCLK to rising edge of CS)
CLKProg = H
5.2.7 Data Setup Time (required t_SUL
20
–
–
ns –
time SI to rising of SCLK)
CLKProg = L
Data Setup Time (required t_SUH
20
–
–
ns –
time SI to falling of SCLK)
CLKProg = H
5.2.8 Data Hold Time (rising edge of t_HL
SCLK to SI)
20
–
–
ns –
CLKProg = L
5.2.9
Data Hold Time (falling edge of t_HH
SCLK to SI)
Disable Time¹⁾
t_DIS
20
–
–
–
–
ns –
200 ns –
CLKProg = H
–
Data Sheet
16
Rev. 2.5, 2010-10-11