TLE4471_09 Datasheet, PDF (16/24 Pages) Infineon Technologies AG – Triple Voltage Regulator

TLE 4471
The reset delay time t_dr is defined by the reset delay capacitor C_DR at pin DR and can be
calculated as follows:
t_rd
=
C_DR
×
V_{-----D---R---,-d--t}
I_DR,ch
(1)
Definitions:
• C_DR = reset delay capacitor
• t_dr = reset delay time required by the application
• V_{DR, dt} = typical 1.8 V for power up reset
• I_{DR, ch} = charge current typical 4 µA
For a delay capacitor C_DR = 100 nF the typical power up reset delay time is 45 ms.
The undervoltage reset circuitry supervises the output voltage. In case V_Q1 falls below
the reset threshold the reset output is set LOW after the reset reaction time t_rr (discharge
of the reset delay capacitor). The reset LOW signal is held down to an output voltage V_Q1
of 1 V. Both, the reset reaction time and the reset delay time are defined by the capacitor
value.
The reset reaction time t_rr is the time it takes the voltage regulator to set its reset output
LOW after the output voltage has dropped below the reset threshold. The reset reaction
time can be calculated using the following equation:
t_rr
=
C_DR
×
V_{-----D---R---,-d---t--–-----}V_{----D---R----,-s--t}
I _{D R ,d i s}
(2)
Data Sheet
16
Rev. 1.6, 2009-02-03