PEB20525 Datasheet, PDF (154/252 Pages) Infineon Technologies AG – 2 Channel Serial Optimized Communication Controller for HDLC/PPP

PEB 20525
PEF 20525
Register Description (CCR3H)
ELC
AFX
CSF
SUET
Enable Length Check
This bit is only valid in HDLC SS7 mode:
If the number of received octets exceeds 272 + 7 within one Signaling
Unit, reception is aborted and bit RSTA.RAB is set.
ELC=’0’
Length Check disabled.
ELC=’1’
Length Check enabled.
Automatic FISU Transmission
This bit is only valid in HDLC SS7 mode:
After the contents of the transmit FIFO (XFIFO) has been transmitted
completely, FISUs are transmited automatically. These FISUs contain
the FSN and BSN of the last transmitted Signaling Unit (provided in
XFIFO).
AFX=’0’
Automatic FISU transmission disabled.
AFX=’1’
Automatic FISU transmission enabled.
Compare Status Field
This bit is only valid in HDLC SS7 mode:
If the status fields of consecutive LSSUs are equal, only the first will be
stored and every following is ignored
CSF=’0’
Compare is disabled, all received LSSUs are stored in the
receive FIFO.
CSF=’1’
Compare is enabled, only the first one of consecutive
equal LSSUs is stored in the receive FIFO.
Signalling Unit Counter Threshold
This bit is only valid in HDLC SS7 mode:
Defines the number of signaling units received in error that will cause an
error rate high indication (ISR1.SUEX).
SUET=’0’ threshold is 64 errored signaling units.
SUET=’1’ threshold is 32 errored signaling units.
Data Sheet
5-154
2000-09-14