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PEB20525 Datasheet, PDF (107/252 Pages) Infineon Technologies AG – 2 Channel Serial Optimized Communication Controller for HDLC/PPP
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PEB 20525
PEF 20525
Register Description
Table 15 Register Overview (cont’d)
Offset Ch
Register
Res
A B read write Val
Meaning
12H 62H STARL
13H 63H STARH
14H 64H
CMDRL
15H 65H
CMDRH
16H 66H
CCR0L
00H Status Register (Low Byte)
10H Status Register (High Byte)
00H Command Register (Low Byte)
00H Command Register (High Byte)
00H Channel Configuration Register 0 (Low
Byte)
17H 67H
CCR0H
00H Channel Configuration Register 0 (High
Byte)
18H 68H
CCR1L
00H Channel Configuration Register 1 (Low
Byte)
19H 69H
CCR1H
00H Channel Configuration Register 1 (High
Byte)
1AH 6AH
CCR2L
00H Channel Configuration Register 2 (Low
Byte)
1BH 6BH
CCR2H
00H Channel Configuration Register 2 (High
Byte)
1CH 6CH
CCR3L
00H Channel Configuration Register 3 (Low
Byte)
1DH 6DH
CCR3H
00H Channel Configuration Register 3 (High
Byte)
1EH 6EH
1FH 6FH
20H 70H
21H 71H
22H 72H
23H 73H
24H 74H
PREAMB
Reserved
ACCM0
ACCM1
ACCM2
ACCM3
UDAC0
00H Preamble Register
00H PPP ASYNC Control Character Map 0
00H PPP ASYNC Control Character Map 1
00H PPP ASYNC Control Character Map2
00H PPP ASYNC Control Character Map 3
7EH User Defined PPP ASYNC Control
Character Map 0
25H 75H
UDAC1
7EH User Defined PPP ASYNC Control
Character Map 1
26H 76H
UDAC2
7EH User Defined PPP ASYNC Control
Character Map 2
Page
131
131
135
135
139
139
143
143
148
148
153
153
157
158
158
159
159
161
161
162
Data Sheet
107
2000-09-14
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