PEB20532 Datasheet, PDF (146/282 Pages) Infineon Technologies AG – 2 Channel Serial Optimized Communication Controller

PEB 20532
PEF 20532
Register Description (CMDRL)
Register 19
CMDRL
Command Register (Low Byte)
CPU Accessibility: read/write
Reset Value:
00_H
Channel A Channel B
Offset Address:
typical usage:
14_H
64_H
written by CPU, evaluated by SEROCCO-M
Bit
7
6
5
4
3
2
1
0
Timer
Transmitter Commands
H
STI
TRES
XIF
XRES
XF
A
STI
TRES TXON XRES
XF
B
STI
TRES
0
XRES
XF
XME
XME
XME
XREP
XREP
XREP
0
TXOFF
0
Register 20
CMDRH
Command Register (High Byte)
CPU Accessibility: read/write
Reset Value:
00_H
Channel A Channel B
Offset Address:
typical usage:
15_H
65_H
written by CPU, evaluated by SEROCCO-M
Bit
7
6
H
RMC
RNR
A
RMC
0
B
RMC
0
5
4
3
2
Receiver Commands
0
0
RSUC
0
0
0
0
0
0
0
HUNT
0
1
0
0
RFRD
RFRD
RRES
RRES
RRES
The command register contains self-clearing command bits. The command bits read a
’1’ until the corresponding command is executed completely.
Data Sheet
5-146
2000-09-14