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| PEB20532 Datasheet, PDF (131/282 Pages) Infineon Technologies AG – 2 Channel Serial Optimized Communication Controller | |||
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PEB 20532
PEF 20532
Register Description (GPIMH)
GPnIM
GPP Pin n Interrupt Mask
(-)
This bit controls the interrupt mask of the corresponding GPP pin:
bit = â0â
Interrupt generation is enabled. An interrupt is generated
on any state transition of the corresponding port pin
(inputs).
bit = â1â
Interrupt generation is disabled (reset value).
Data Sheet
5-131
2000-09-14
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