TLE4278G_07 Datasheet, PDF (14/20 Pages) Infineon Technologies AG – 5-V Low Drop Fixed Voltage Regulator Output voltage tolerance ≤ ±2%

TLE 4278 G
Watchdog Timing
The frequency of the watchdog pulses has to be higher than the minimum pulse
sequence which is set by the external reset delay capacitor C_D. Calculation can be done
according to the formulas given in Figure 8.
The watchdog output is internally connected to the output Q via a 30 kΩ pull-up resistor.
To generate a watchdog created reset signal for the microcontroller the pin WO can be
connected to the reset input of the microcontroller. It is also allowed to parallel the
watchdog out to the reset out.
V_WΙ
V_Ι
t
V_Q
T_{WD, p}
t
V_D
V_DU
V_DWL
V_WO
T_{WI, tr}
t
t _{WD, L}
t
T_WI,
tr
=
(V_DU -V_DWL
Ι _{D, wd}
)
C
D
;
T_WD,
p
=
(V_DU
-V_DWL )
Ι _{D, wc}
(Ι _{D, wc}+
x Ι _{D, wd}
Ι
D,
wd⁾
C
D
;
t
WD,
L
=
(V_DU -V_DWL
Ι _{D, wc}
)
C_D
t
AED03099
Figure 8 Timing of the Watchdog Function
Data Sheet
14
Rev. 1.4, 2007-02-19