TLE4278G_07 Datasheet, PDF (11/20 Pages) Infineon Technologies AG – 5-V Low Drop Fixed Voltage Regulator Output voltage tolerance ≤ ±2%

TLE 4278 G
Reset Timing
The power-on reset delay time is defined by the charging time of an external capacitor
C_D which can be calculated as follows:
C_D = (∆t_rd × I_D,c)/∆V
(1)
Definitions:
• C_D = delay capacitor
• ∆t_rd = delay time
• I_D,c = charge current, typical 5 µA
• ∆V = V_DU, typical 1.9 V
• V_DU = upper delay switching threshold at C_D for reset delay time
The reset reaction time t_rr is the time it takes the voltage regulator to set the reset out
LOW after the output voltage has dropped below the reset threshold. It is typically 1 µs
for delay capacitor of 47 nF. For other values for C_D the reaction time can be estimated
using Equation (2):
t_rr ≈ 20 s/F × C_D
(2)
V_Ι
V_Q
V_D
t _rd
t _rr
V_RO
t
< t _rr
V _{Q, rt}
dV
dt
=
Ι _D,c
C_D
t
V _DU
V _DRL
t
Power-on-Reset
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage Secondary Overload
Spike at Output
Figure 5 Reset Timing (watchdog disabled)
t
AED03010
Data Sheet
11
Rev. 1.4, 2007-02-19