SAK82C900 Datasheet, PDF (14/29 Pages) Infineon Technologies AG – Standalone TwinCAN Controller

82C900
Preliminary
Register Address Map
All Shell and Kernel registers, implemented for controlling the 82C900 device, are
summarized in Table 0-1; detailed information about each register is provided in the
respective module description chapter.
Note: Accesses to addresses which are not specified as registers in the following
register address map are forbidden.
Table 0-1 Summary of Registers
Register Name
Standalone Shell Registers
Global Device Control Register
Interrupt Control Register
CAN Clock Control Register
Input/Output Mode Register 0
Input/Output Mode Register 2
Input/Output Mode Register 4
Input Value Register (8-bit port)
Output Value Register (8-bit port)
CAN Power-Down Control Register
CAN Input/Output Control Register
CAN Initialization Control Register
Paging Mode Register
(accessible in all pages)
CAN RAM Address Buffer Register
Initialization Control Register
TwinCAN Kernel, Common Registers
CAN Receive Interrupt Pending Register
CAN Transmit Interrupt Pending Register
TwinCAN Kernel, Node A Registers
CAN Node A Control Register
CAN Node A Status Register
CAN Node A Interrupt Pending Register
CAN Node A Bit Timing Register
Register
Symbol
GLOBCTR
INTCTR
CLKCTR
IOMODE0
IOMODE2
IOMODE4
INREG
OUTREG
CANPWD
CANIO
CANINIT
PAGE
CAB
INITCTR
RXIPND
TXIPND
ACR
ASR
AIR
ABTR
Address Reset Value
1)
0010_H
0012_H
0014_H
0020_H
0022_H
0024_H
0026_H
0028_H
0040_H
0042_H
0044_H
XX7C_H
A0 00_H
00 00_H
00 24_H
00 00_H
00 00_H
00 00_H
00 00_H
00 00_H
00 00_H
00 00_H
00 00_H
00 00_H
007E_H
02F0_H
00 00_H
0103 0000_H
0284_H
0288_H
0000 0000_H
0000 0000_H
0200_H
0204_H
0208_H
020C_H
0000 0001_H
0000 0000_H
0000 0000_H
0000 0000_H
Data Sheet
14
V 1.0D3, 2001-03