ICE3A1065 Datasheet, PDF (14/32 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/ Depletion CoolMOS™

CoolSET™-F3
Functional Description
3.5
Current Limiting
PWM Latch
FF1
Propagation-Delay
Compensation
Current Limiting
3.5.1
Leading Edge Blanking
V_Sense
V_csth
t_LEB = 220ns
PWM-OP
&
G10
Active Burst
Mode
C10
V_csth
Leading
Edge
Blanking
220ns
C12
0.257V
10k
1pF
D1
CS
Figure 12 Current Limiting Block
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
internal CoolMOS™ is sensed via an external sense
resistor R_Sense . By means of R_Sense the source current
is transformed to a sense voltage V_Sense which is fed
into the pin CS. If the voltage V_Sense exceeds the
internal threshold voltage V_csth the comparator C10
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the internal CoolMOS™ in case of Current
Limiting. The influence of the AC input voltage on the
maximum output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
t
Figure 13 Leading Edge Blanking
Each time when the internal CoolMOS™ is switched
on, a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. This spike can cause the gate
drive to switch off unintentionally. To avoid a premature
termination of the switching pulse, this spike is blanked
out with a time constant of t_LEB = 220ns. During this
time, the gate drive will not be switched off.
3.5.2
Propagation Delay Compensation
In case of overcurrent detection, the switch-off of the
internal CoolMOS™ is delayed due to the propagation
delay of the circuit. This delay causes an overshoot of
the peak current I_peak which depends on the ratio of dI/
dt of the peak current (see Figure 14).
I_Sense
I_peak2
I_peak1
I_Limit
Signal1
I_Overshoot2
Signal2
t_{Propagation Delay}
I_Overshoot1
t
Figure 14 Current Limiting
The overshoot of Signal2 is bigger than of Signal1 due
to the steeper rising waveform. This change in the
slope is depending on the AC input voltage.
Propagation Delay Compensation is integrated to limit
the overshoot dependency on dI/dt of the rising primary
current. That means the propagation delay time
between exceeding the current sense threshold V_csth
and the switch off of the internal CoolMOS™ is
compensated over temperature within a wide range.
Version 2.3
14
02 Apr 2013