ICE3A1065 Datasheet, PDF (13/32 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controller with integrated 650V Startup Cell/ Depletion CoolMOS™

CoolSET™-F3
3.4
PWM Section
Functional Description
3.4.3
Gate Driver
0.72
Oscillator
Duty Cycle
max
Clock
PWM Section
VCC
PWM-Latch
1
Soft Start
Comparator
PWM
Comparator
Current
Limiting
FF1
1
S
Gate Driver
G8
RQ
&
G9
Internal
CoolMOS™
Gate
Figure 9 PWM Section
Gate
CoolMOS™
Gate Driver
Figure 10 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the internal
CoolMOS™ threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 11).
3.4.1
Oscillator
The oscillator generates a fixed frequency. The
switching frequency of ICE3Axx65x is f_OSC = 100kHz
and for ICE3Bxx65x f_OSC = 67kHz. A resistor, a
capacitor and a current source and current sink which
determine the frequency are integrated. The charging
and discharging current of the implemented oscillator
capacitor are internally trimmed, in order to achieve a
very accurate switching frequency. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of D_max=0.72.
3.4.2
PWM-Latch FF1
The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the internal CoolMOS™
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator or
the Current-Limit comparator. In case of resetting, the
driver is shut down immediately.
(internal) V_Gate
ca. t = 130ns
5V
t
Figure 11 Gate Rising Slope
Thus the leading switch on spike is minimized. When
the integrated CoolMOS™ is switched off, the falling
shape of the driver is slowed down when reaching 2V
to prevent an overshoot below ground. Furthermore the
driver circuit is designed to eliminate cross conduction
of the output stage.
During powerup when VCC is below the undervoltage
lockout threshold V_VCCoff, the output of the Gate Driver
is low to disable power transfer to the seconding side.
Version 2.3
13
02 Apr 2013