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BTS5480SF Datasheet, PDF (14/59 Pages) Infineon Technologies AG – SPI Power Controller
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SPOC - BTS5480SF
Power Supply
Activating one of the outputs via the input pins (INx = high) will wake-up the device out of stand-by mode. The
power stages are working without VDD supply according to the table above. The output turn-on times will be
extended by the stand-by channel wake up time tWU(STCH) as long as no other channel is active. If one channel is
active already before channel turn-on times ton (6.6.12) can be considered.
Note: In the operation with VDD = 0 V and INx = high a switching off of all input signals will turn the device in stand-
by mode. In stand-by mode the error latches are cleared.
Limp home (LHI = high) applied for a time longer than tLH(ac) will wake-up the device out of stand-by mode after
the power-on wake up time tWU(PO) and it is working without VDD supply. Channels 1, 2 and 3 can be activated via
the input pins INx. The error latches can be cleared by a low-high transition at the according input pin.
5.2
Reset
There are several reset trigger implemented in the device. They reset the SPI registers including the over
temperature latches to their default values. The power stages will switch off, if they are activated via the SPI
register OUT.n. If the power stages are activated via the parallel input pins they are not affected by the reset
signals. The ERR-flags are cleared by those reset triggers. The over temperature protection and latches are
functional after a reset trigger.
Note: During a reset only the channels 1, 2 and 3 can be activated via the according input pins. The input assigned
mode is not available during a reset.
The first SPI transmission after any kind of reset contains at pin SO the read information from the standard
diagnosis, the transmission error bit TER is set.
Power-On Reset
The power-on reset is released, when VDD voltage level is higher than VDD(PO). The SPI interface can be accessed
after wake up time tWU(PO).
Reset Command
There is a reset command available to reset all register bits of the register bank and the diagnosis registers. As
soon as HWCR.RST = 1b, a reset is triggered equivalent to power-on reset. The SPI interface can be accessed
after transfer delay time tCS(td).
Limp Home Mode
The limp home mode will be activated as soon as the pin LHI is set to high for a time longer than tLH(ac). The SPI
write-registers are reset with applied VBB voltage. The outputs OUTx can be activated via the input pins also during
activated limp home mode. The error latches can be cleared by a low-high transition at the according input pin.
For application example see Figure 26. The SPI interface is operating normally, so the limp home register bit LHI
as well as the error flags can be read, but any write command will be ignored.
Data Sheet
14
Rev. 1.0, 2010-04-12
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