ICE3AR2280VJZ Datasheet, PDF (13/43 Pages) Infineon Technologies AG – Of f -Line SMPS Cur rent Mode Cont rol ler wi th integrated 800V

CoolSET™ F3R80
ICE3AR2280VJZ
Functional Description
The primary current is sensed by the external series resistor R_Sense inserted in the source of the integrated
CoolMOS™. By means of Current Mode regulation, the secondary output voltage is insensitive to the line variations.
The current waveform slope will change with the line variation, which controls the duty cycle.
The external R_Sense allows an individual adjustment of the maximum source current of the integrated
CoolMOS™.
To improve the Current Mode during light load conditions the amplified current ramp of the PWM-OP is
superimposed on a voltage ramp, which is built by the switch T2, the voltage source V1 and a resistor R1 (see
Figure 7). Every time the oscillator shuts down for maximum duty cycle limitation the switch T2 is closed by V_OSC.
When the oscillator triggers the Gate Driver, T2 is opened so that the voltage ramp can start.
Soft-Start Comparator
PWM Comparator
FBB
Oscillator
C8
PWM-Latch
V_OSC
T₂
time delay
circuit (156ns)
Gate Driver
0.6V
10k
R₁
V₁
X3.25
PWM OP
Voltage Ramp
Figure 7:
Improved Current Mode
In case of light load the amplified current ramp is too small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the comparison with the FBB-signal. The duty cycle is then controlled
by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by the inverted VOSC signal, the Gate Driver is switched-off until it
reaches approximately 156ns delay time (Figure 8). It allows the duty cycle to be reduced continuously till 0% by
decreasing VFBB below that threshold.
V_OSC
max.
Duty Cycle
Voltage
t
Ramp
0.6V
FBB
Gate
t
Driver
156ns time delay
t
Figure 8:
Light Load Conditions
Data Sheet
13
V2.1, 2013-10-22