TLE6711 Datasheet, PDF (12/28 Pages) Infineon Technologies AG – Multifunctional Voltage Regulator and Watchdog

TLE 6711
Circuit Description
2
Circuit Description
Below some important sections of the TLE 6711 are described in more detail.
2.1
Power On Reset
In order to avoid any system failure, a sequence of several conditions has to be passed.
In case of V_CC power down (V_CC < V_RT for t > t_RR) a logic LOW signal is generated at the
pin RO to reset an external microcontroller. When the level of V_CC reaches the reset
threshold V_RT, the signal at RO remains LOW for the Power-up reset delay time t_RD
before switching to HIGH. If V_CC drops below the reset threshold V_RT for a time extending
the reset reaction time t_RR, the reset circuit is activated and a power down sequence of
period t_RD is initiated. The reset reaction time t_RR avoids wrong triggering caused by short
“glitches” on the V_CC-line.
V_CC
< t_RR
< t_RD
typ. 4.65 V
V_RT
1V
Start-Up ON Delay
RO
H
Invalid
L
Power Start-Up
t_RD
Normal
ON Delay
Started
ON Delay
Stopped
Invalid
t_RR
Failed
Invalid
N Failed
t
t_RD
t
Normal
AET02950
Figure 3 Reset Function
2.2
Watchdog Operation
The watchdog uses one hundred of the oscillator’s clock signal period as a timebase,
defined as the watchdog cycle time t_CYL.
After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW
for the reset delay time t_RD, i.e. 64 cycles. With the LOW to HIGH transition of the signal
at RO the device starts the closed window time t_CW = 32 cycles. A trigger signal within
this window is interpreted as a pretrigger failure according to the figures shown below.
After the closed window the open window with the duration t_OW is started. The open
Data Sheet V 2.22
12
2001-04-23