XMC4700 Datasheet, PDF (106/130 Pages) Infineon Technologies AG – Microcontroller Series for Industrial Applications

Preliminary
Multiplexed Write Timing
XMC4700 / XMC4800
XMC4000 Family
Electrical Parameters
EBU
STATE
Duration Limits in
EBU_CLK Cycles
Address
Phase
1...15
Address Hold
Phase (opt.)
0...15
Command
Phase
1...31
Data Hold
Phase
0...15
Recovery New Addr.
Phase (opt.) Phase
0...15
1...15
A[max:16]¹⁾
CS[3:0]
CSCOMB
ADV
pv + t_a
Valid Address
pv + t₃₀
pv + t_a
pv + t₃₃
pv + t₃₂
pv + t₃₁
Next
Addr.
pv + t₃₉
RD
RD/WR
BC[3:0]
pv + t_a
pv + t_a
t34
pv + t_a
WAIT
t35
t36
AD[31:0]²⁾
pv + t₁₃
pv + t₁₄
Address Out
pv + t37
pv + t₃₈
Data Out
1) _{For 16-bit MUX and Twin 16-bit MUX only}
2)_{* 16-bit MUX:}
- Address A[15:0], Data D[15:0] on pins AD[15:0] only
* Twin 16-Bit MUX: - Address A[15:0] on pins AD[15:0] and AD[31:16] in parallel
- Data D[31:0] on pins AD[31:0]
* 32-bit MUX:
- Address A[24:0] on pins AD[24:0]
- Data D[31:0] on pins AD[31:0]
pv = programmed value,
TEBU_CLK * sum (corresponding bitfield values)
EBU_MuxWR_Async.vsd
Figure 43 Multiplexed Write Access
Data Sheet
106
V0.7, 2015-10
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