TLE8088EM Datasheet, PDF (10/24 Pages) Infineon Technologies AG – Engine management IC for Small Engines

TLE 8088 EM
Voltage Regulator
Vs
V_V5DD
VRT
< tRR
V NRO
TRD
V_{NRO_H}
V _{NRO_L}
Figure 4 Reset Function and Timing Diagram
t
tRR
tRR
t
T RD
t
5.3
Watchdog Operation
After power on, the reset output signal at the NRO pin is kept LOW for the power-on reset delay time T_RD of typ.
15ms. With the LOW to HIGH transition of the signal at NRO the micro controller reset is released.
The TLE8088EM integrates a watchdog function. If WDE is connected to low, the watchdog function is disabled.
If the WDE is connected to 5V or left open, the watchdog function is enabled. A pull up current source is integrated
in the WDE pin.
After the activation of the watchdog function, the timing of the signal on WDI from the micro-controller must
correspond the WD-Period T_WD,p specified in the electrical characteristics. A Re-Trigger of the WD-Period is done
with a HIGH-to-LOW transition at the WDI-pin within the time T_WD,p.
A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken as a trigger. To avoid wrong triggering
due to parasitic glitches two HIGH samples followed by two LOW samples (sample period t_sam typ. 64μs ) are
decoded as a valid trigger, see Figure 6. A reset is generated (NRO goes LOW) for the time T_WR if there is no
trigger pulse during the Watchdog Period as shown in Figure 5.
Data Sheet
10
Rev 1.0, 2012-10-01