TLE4678_15 Datasheet, PDF (10/37 Pages) Infineon Technologies AG – Low Drop Out Linear Voltage Regulator

TLE4678
General Product Characteristics
4.3
Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards.
For more information, go to www.jedec.org.
Parameter
Symbol
Limit Values Unit Conditions
Number
Min. Typ. Max.
TLE4678GM (PG-DSO-14)
Junction – Soldering Point R_thJSP –
Junction – Ambient
R_thJA
–
–
27 –
104 –
73 –
K/W Pins 3 - 5 and 10 - 12
fixed to T_A ¹⁾
K/W Footprint only ^{1) 2)}
K/W 300 mm² PCB
heatsink area ^{1) 2)}
4.3.1
4.3.2
4.3.3
–
65 –
K/W 600 mm² PCB
heatsink area ^{1) 2)}
4.3.4
–
63 –
K/W 2s2p PCB ^{1) 3)}
4.3.5
TLE4678EL (PG-SSOP-14)
Junction to Case
Junction to Ambient
R_thJC
–
R_thJA
–
–
10 –
140 –
63 –
K/W – ¹⁾
K/W Footprint only ^{1) 2)}
K/W 300mm² PCB
heatsink area ^{1) 2)}
4.3.6
4.3.7
4.3.8
–
53 –
K/W 600mm² PCB
heatsink area ^{1) 2)}
4.3.9
–
47 –
K/W 2s2p PCB ^{1) 3)}
4.3.10
1) Not subject to production test; specified by design.
2) Specified R_thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
3) Specified R_thJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm
Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
Datasheet
10
Rev. 1.2, 2014-10-17