TLE42794_14 Datasheet, PDF (10/32 Pages) Infineon Technologies AG – Very low Current Consumption

4.3
Thermal Resistance
TLE42794
General Product Characteristics
Table 3 Thermal Resistance
Parameter
Symbol
Values
Unit Note / Test Condition Number
Min. Typ. Max.
TLE42794G (PG-DSO-8)
Junction to Soldering Point¹⁾
Junction to Ambient¹⁾
Junction to Ambient¹⁾
Junction to Ambient¹⁾
R_thJSP
–
R_thJA
–
R_thJA
–
R_thJA
–
80 –
113 –
172 –
142 –
K/W measured to pin 5
K/W FR4 2s2p board²⁾
P_4.3.1
P_4.3.2
K/W FR4 1s0p board,
footprint only³⁾
P_4.3.3
K/W FR4 1s0p board,
P_4.3.4
300mm² heatsink area
on PCB³⁾
Junction to Ambient¹⁾
R_thJA
–
136 –
K/W FR4 1s0p board,
P_4.3.5
600mm² heatsink area
on PCB³⁾
TLE42794GM (PG-DSO-14)
Junction to Soldering Point¹⁾
Junction to Ambient¹⁾
Junction to Ambient¹⁾
Junction to Ambient¹⁾
R_thJSP
–
R_thJA
–
R_thJA
–
R_thJA
–
27 –
63 –
104 –
73 –
K/W measured to group of P_4.3.6
pins 3, 4, 5, 10, 11, 12
K/W FR4 2s2p board²⁾
P_4.3.7
K/W FR4 1s0p board,
footprint only³⁾
P_4.3.8
K/W FR4 1s0p board,
P_4.3.9
300mm² heatsink area
on PCB³⁾
Junction to Ambient¹⁾
R_thJA
–
65 –
K/W FR4 1s0p board,
P_4.3.10
600mm² heatsink area
on PCB³⁾
TLE42794E (PG-SSOP-14 exposed pad)
Junction to Case¹⁾
R_thJC
–
Junction to Ambient¹⁾
Junction to Ambient¹⁾
R_thJA
–
R_thJA
–
Junction to Ambient¹⁾
R_thJA
–
10 –
47 –
145 –
63 –
K/W measured to Exposed P_4.3.11
Pad
K/W FR4 2s2p board²⁾
P_4.3.12
K/W FR4 1s0p board,
footprint only³⁾
P_4.3.13
K/W FR4 1s0p board,
P_4.3.14
300mm² heatsink area
on PCB³⁾
Junction to Ambient¹⁾
R_thJA
–
53 –
K/W FR4 1s0p board,
P_4.3.15
600mm² heatsink area
on PCB³⁾
1) not subject to production test, specified by design
2) Specified R_thJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
3) Specified R_thJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm³ board with 1 copper layer (1 x 70µm Cu).
Data Sheet
10
Rev. 1.2, 2014-07-03