ICE3AR10080JZ Datasheet, PDF (10/34 Pages) Infineon Technologies AG – Off-Line SMPS Current Mode Controllerwith integrated 800V CoolMOS® and Startup cell (brownout & frequency jitter) in DIP-7

CoolSET^®-F3R80
ICE3AR10080JZ
Functional Description
7). It allows the duty cycle to be reduced continuously
till 0% by decreasing V_FBB below that threshold.
V_OSC
max.
Duty Cycle
FBB
5V
R_FB
Soft-Start Comparator
PWM-Latch
C8
Voltage
Ramp
0.6V
FBB
Gate
Driver
156ns time delay
t
Optocoupler
t
PWM Comparator
0.6V
PWM OP
CS
X3.25
Improved
Current Mode
t ^{Figure 8 PWM Controlling}
Figure 7 Light Load Conditions
3.4
3.3.1 PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
R_Sense connected to pin CS. R_Sense converts the source
current into a sense voltage. The sense voltage is
amplified with a gain of 3.25 by PWM OP. The output
of the PWM-OP is connected to the voltage source V₁.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (Figure
8).
3.3.2 PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOS^® with the feedback
signal V_FBB (Figure 8). V_FBB is created by an external
optocoupler or external transistor in combination with
the internal pull-up resistor R_FB and provides the load
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS^®
exceeds the signal V_FBB the PWM-Comparator
switches off the Gate Driver.
Startup Phase
Soft Start counter
SoftS
Soft Start
Soft Start
Soft-Start
C om parator
C7
&
G7
Gate Driver
0.6V
x3.25
CS
PWM OP
Figure 9 Soft Start
Version 2.2a
10
11 Jan 2012