HYS64V8200GDL Datasheet, PDF (10/15 Pages) Infineon Technologies AG – 144 pin SO-DIMM SDRAM Modules

HYS64V8200GDL/HYS64V16220GDL
144 pin SO-DIMM SDRAM Modules
Notes:
1. All AC characteristics shown are for SDRAM components.
An initial pause of 100µs is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
2. AC timing tests have V_il = 0.4 V and V_ih = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V_ih and V_il. All AC measurements assume t_T=1ns
with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V
..
CLOCK 1.4 V
tCH
2.4 V
0.4 V
t CL
tT
t IS
t IH
INPUT
OUTPUT
1.4 V
tAC
t LZ
tAC
t OH
t HZ
1.4 V
IO.vsd
I/O
50 pF
Measurement conditions for
tac and toh
3. If clock rising time is longer than 1ns, a time (t_T -0.5) ns has to be added to this parameter.
4. If t_T is longer than 1ns, a time (t_T -1) ns has to be added to this parameter.
5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh
commands must be given to “wake-up“ the device.
6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
7. Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
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