IDT82V3202 Datasheet, PDF (93/117 Pages) Integrated Device Technology – EBU WAN PLL

IDT82V3202
EBU WAN PLL
6.2.9 PBO & PHASE OFFSET CONTROL REGISTERS
PHASE_MON_PBO_CNFG - Phase Transient Monitor & PBO Configuration
Address:78H
Type: Read / Write
Default Value: 0X000110
7
6
IN_NOISE_WIN
DOW
-
5
PH_MON_EN
4
3
2
1
0
PH_MON_PBO PH_TR_MON_L PH_TR_MON_L PH_TR_MON_L PH_TR_MON_L
_EN
IMT3
IMT2
IMT1
IMT0
Bit
Name
Description
This bit determines whether the input clock whose edge respect to the reference clock is outside ±5% is enabled to be
7
IN_NOISE_WINDOW
selected for T0 DPLL.
0: Disabled. (default)
1: Enabled.
6
-
Reserved.
This bit is valid only when the PH_MON_PBO_EN bit (b4, 78H) is ‘1’. It determines whether the Phase Transient Monitor
5
PH_MON_EN
is enabled to monitor the phase-time changes on the T0 selected input clock.
0: Disabled. (default)
1: Enabled.
This bit determines whether a PBO event is triggered when the phase-time changes on the T0 selected input clock are
greater than a programmable limit over an interval of less than 0.1 seconds with the PH_MON_EN bit being ‘1’. The limit
4
PH_MON_PBO_EN is programmed by the PH_TR_MON_LIMT[3:0] bits (b3~0, 78H).
0: Disabled. (default)
1: Enabled.
These bits represent an unsigned integer. The Phase Transient Monitor limit in ns can be calculated as follows:
3-0
PH_TR_MON_LIMT[3:0] _{Limit (ns) = (PH_TR_MON_LIMT[3:0] + 7) X 156.}
Programming Information
93
September 11, 2009