IDT82V3202 Datasheet, PDF (8/117 Pages) Integrated Device Technology – EBU WAN PLL

List of Figures
Figure 1. Functional Block Diagram ............................................................................................................................................................................ 11
Figure 2. Pin Assignment (NL68 Top View) ................................................................................................................................................................ 12
Figure 3. Pin Assignment (TQFP 64 Top View) .......................................................................................................................................................... 13
Figure 4. Pre-Divider for An Input Clock ..................................................................................................................................................................... 20
Figure 5. Input Clock Activity Monitoring ..................................................................................................................................................................... 21
Figure 6. External Fast Selection ................................................................................................................................................................................ 23
Figure 7. T0 Selected Input Clock vs. DPLL Automatic Operating Mode ................................................................................................................... 29
Figure 8. On Target Frame Sync Input Signal Timing ................................................................................................................................................. 38
Figure 9. 0.5 UI Early Frame Sync Input Signal Timing .............................................................................................................................................. 38
Figure 10. 0.5 UI Late Frame Sync Input Signal Timing .............................................................................................................................................. 39
Figure 11. 1 UI Late Frame Sync Input Signal Timing ................................................................................................................................................. 39
Figure 12. Line Card Application ................................................................................................................................................................................. 41
Figure 13. Data Transfer on the I2C-bus ..................................................................................................................................................................... 42
Figure 14. Slave-receiver Mode ................................................................................................................................................................................... 43
Figure 15. Slave-transmitter Mode .............................................................................................................................................................................. 43
Figure 16. Address Assignment ................................................................................................................................................................................... 44
Figure 17. Timing Definition of I2C-bus ....................................................................................................................................................................... 44
Figure 18. JTAG Interface Timing Diagram ................................................................................................................................................................. 46
Figure 19. Assembly for Expose Pad thermal Release Path (Side View) ................................................................................................................... 96
Figure 20. Recommended PECL Output Port Line Termination ................................................................................................................................ 100
Figure 21. Recommended LVDS Output Port Line Termination ................................................................................................................................ 101
Figure 22. Output Wander Generation ...................................................................................................................................................................... 105
Figure 23. Input / Output Clock Timing ...................................................................................................................................................................... 106
Figure 24. 68-Pin NL Package Dimensions (a) (in Millimeters) ................................................................................................................................. 112
Figure 25. 68-Pin NL Package Dimensions (b) (in Millimeters) ................................................................................................................................. 113
Figure 26. 64-Pin EDG Package Dimensions (a) (in Millimeters) .............................................................................................................................. 114
Figure 27. 64-Pin EDG Package Dimensions (b) (in Millimeters) .............................................................................................................................. 115
Figure 28. EDG64 Recommended Land Pattern with Exposed Pad (in Millimeters) ................................................................................................. 116
List of Figures
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September 11, 2009