IDT82P2828 Datasheet, PDF (90/154 Pages) Integrated Device Technology – 28(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
RJA - Receive Jitter Attenuation Configuration Register
Address: 003H, 043H, 083H, 0C3H, 103H, 143H, 183H, 1C3H, (CH1~CH8)
203H, 243H, 283H, 2C3H, 303H, 343H, 383H, 3C3H, (CH9~CH16)
403H, 443H, 483H, 4C3H, 503H, 543H, 583H, 5C3H, (CH17~CH24)
603H, 643H, 683H, 6C3H, (CH25~CH28)
7C3H (CH0)
Type: Read / Write
Default Value: 00H
7
6
5
4
-
-
-
RJA_LIMT
3
RJA_EN
2
RJA_DP1
1
RJA_DP0
0
RJA_BW
Bit
Name
Description
7-5
-
Reserved.
4
RJA_LIMT This bit determines whether the JA-Limit function is enabled in the RJA.
0: Disable. (default)
1: Enable. The speed of the RJA outgoing data will be adjusted automatically if the FIFO in the RJA is 2-bit close to its full or
emptiness.
3
RJA_EN This bit controls whether the RJA is enabled to use.
0: Disable. (default)
1: Enable.
2-1
RJA_DP[1:0] These bits select the depth of the RJA FIFO.
00: 128-bit. (default)
01: 64-bit.
1X: 32-bit.
0
RJA_BW This bit selects the Corner Frequency for the RJA.
0: 5 Hz (in T1/J1 mode) / 6.77 Hz (in E1 mode). (default)
1: 1.26 Hz (in T1/J1 mode) / 0.87 Hz (in E1 mode).
Programming Information
90
January 11, 2007