IDT82P2828 Datasheet, PDF (143/154 Pages) Integrated Device Technology – 28(+1) Channel High-Density T1/E1/J1 Line Interface Unit

IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
8.13.3 PARALLEL INTEL NON-MULTIPLEXED MICROPROCESSOR INTERFACE
8.13.3.1Read Cycle Specification
Symbol
t_SAR
t_RSW
t_HAR
t_PRD
t_ZRD
Parameter
Address to valid read setup time
Valid read signal width
Address to valid read hold time
Data propagation delay after valid read signal falling edge
Valid read negated to output High-Z
Min
5
36 (T1/J1) / 33 (E1) or wait until RDY acti-
vated
0
5
MAX
31 (T1/J1) / 28 (E1)
20
Units
ns
ns
ns
ns
ns
tSAR
tHAR
A[x:0]
Valid address
tRSW
RD + CS
tPRD
tZRD
D[7:0]
Valid Data
RDY
Note: WR shall be tied to high.
Figure-64 Parallel Intel Non-Multiplexed Microprocessor Interface Read Cycle
Physical And Electrical Specifications
143
January 11, 2007