IDT70V9189 Datasheet, PDF (9/17 Pages) Integrated Device Technology – HIGH-SPEED 3.3V 64/32K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

IDT70V9189/79L
High-Speed 64/32K x 9 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read^(1,2)
tCYC2
tCH2
tCL2
CLK
tSA tHA
ADDRESS(B1)
A0
A1
A2
A3
A4
A5
A6
CE0(B1)
tSC tHC
tSC tHC
DATAOUT(B1)
ADDRESS(B2)
tSA tHA
A0
tCD2
A1
tCD2
Q0
tDC
A2
tCKHZ⁽³⁾
Q1
tDC
A3
tCD2
tCKLZ ⁽³⁾
A4
Q3
tCKHZ⁽³⁾
A5
A6
CE0(B2)
tSC tHC
DATAOUT(B2)
tSC tHC
tCD2
tCKLZ⁽³⁾
tCKHZ⁽³⁾
Q2
tCD2
Q4
tCKLZ ⁽³⁾
4860 drw 08
Timing Waveform of a Bank Select Flow-Through Read⁽⁶⁾
tCYC1
tCH1
tCL1
CLK
tSA tH
A
ADDRESS(B1)
A0
A1
A2
A3
A4
A5
A6
CE0(B1)
DATAOUT(B1)
ADDRESS(B2)
tSC tHC
tCD1
tSA tHA
A0
tSC tHC
tCD1
D0
tDC
tCKHZ⁽¹⁾
D1
tDC
A1
A2
tCD1
tCKLZ ⁽¹⁾
A3
D3
tCKHZ⁽¹⁾
tCD1
D5
tCKLZ⁽¹⁾
A4
A5
A6
CE0(B2)
tSC tHC
DATAOUT(B2)
tSC tHC
tCD1
tCKLZ⁽¹⁾
tCKHZ⁽¹⁾
D2
tCD1
tCKLZ⁽¹⁾
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9089/79 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.492
tCKHZ ⁽¹⁾
D4
,
4860 drw 08a