ICS871004I-04 Datasheet, PDF(9/15 Page) Integrated Device Technology – DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

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ICS871004I-04 Datasheet, PDF (9/15 Pages) Integrated Device Technology – DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

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ICS871004I-04

DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESSâ¢ JITTER ATTENUATOR

APPLICATION INFORMATION

PRELIMINARY

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. To achieve optimum jitter per-

formance, power supply isolation is required. The ICS871004I-

04 provides separate power supplies to isolate any high switch-

ing noise from the outputs to the internal PLL. VDD, VDDA and VDDO

should be individually connected to the power supply

plane through vias, and 0.01ÂµF bypass capacitors should be used

for each pin. Figure 1 illustrates this for a generic VDD pin and also

shows that VDDA requires that an additional10Î© resistor

along with a 10ÂµF bypass capacitor be connected to the VDDA pin.

VDD

VDDA

3.3V

.01Î¼F 10Î©

.01Î¼F

10Î¼F

FIGURE 1. POWER SUPPLY FILTERING

RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS

INPUTS:

LVCMOS CONTROL PINS

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1kÎ© resistor can be used.

OUTPUTS:

DIFFERENTIAL OUTPUTS

All unused differential outputs can be left floating. We recommend

that there is no trace attached. Both sides of the differential output

pair should either be left floating or terminated.

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V /2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

and R2/R1 = 0.609.

VDD

Single Ended Clock Input

V_REF

0.1u

CLK

nCLK

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

IDTâ¢ / ICSâ¢ 0.7V DIFFERENTIAL JITTER ATTUNUATOR

ICS871004AGI-04 REV A JANUARY 17, 2008

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