ICS871004I-04 Datasheet, PDF (1/15 Pages) Integrated Device Technology – DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR

PRELIMINARY
DIFFERENTIAL-TO-0.7V DIFFERENTIAL
PCI EXPRESS™ JITTER ATTENUATOR
ICS871004I-04
GENERAL DESCRIPTION
The ICS871004I-04 is a high performance
ICS
Differential-to-0.7V Differential Jitter Attenuator
HiPerClockS™ _{designed for use in PCI Express™ systems. In some}
PCI Express systems, such as those found in
desktop PCs, the PCI Express clocks are
generated from a low bandwidth, highphase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may
be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer and
from the system board. The ICS871004I-04 has 3 PLL
bandwidth modes: 200kHz, 400kHz and 800kHz. The 200kHz
mode will provide maximum jitter attenuation, but with higher
PLL tracking skew and spread spectrum modulation from the
motherboard synthesizer may be attenuated. The 400kHz
provides an intermediate bandwidth that can easily track tri-
angular spread profiles, while providing good jitter attenuation.
The 800kHz bandwidth provides the best tracking skew and
will pass most spread profiles, but the jitter attenuation will not
be as good as the lower bandwidth modes. The ICS871004I-
04 can be set for different modes using the F_SEL pins as
shown in Table 3C.
Features
• Four 0.7V differential output pairs
• One differential clock input
• CLK and nCLK supports the following input types: LVPECL,
LVDS, LVHSTL, SSTL, HCSL
• Output frequency range: 98MHz - 640MHz
• Input frequency range: 98MHz - 128MHz
• VCO range: 490MHz - 640MHz
• Cycle-to-cycle jitter: 19ps (typical)
• Additive phase jitter, RMS: 0.23ps (typical)
• 3.3V operating supply
• Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free
(RoHS 6) packages
The ICS871004I-04 uses IDT’s 3^rd Generation FemtoClock^TM PLL
technology to achieve the lowest possible phase noise. The device
is packaged in a 24 Lead TSSOP package, making it ideal for
use in space constrained applications such as PCI Express add-
in cards.
BLOCK DIAGRAM
IREF
+-
PLL BANDWIDTH
BW_SEL[1:0]
0 0 = PLL Bandwidth: ~200kHz
0 1 = PLL Bandwidth: ~400kHz (default)
1 0 = PLL Bandwidth: ~800kHz
1 1 = PLL BYPASS
PIN ASSIGNMENT
OE ^Pullup
F_SEL[1:0] ^Pulldown
BW_SEL[1:0] ^{Pulldown:Pullup}
CLK ^Pulldown
nCLK ^Pullup
MR ^Pulldown
2
2
Control
Logic
Phase
VCO
Detector ^{490 - 640MHz}
÷5
M _{0 0 ÷5}
U
(default)
X _{0 1 ÷4}
1 0 ÷2
1 1 ÷1
nQ0 1
24 Q0
nQ2 2
23 VDD
Q2 3
22 Q1
VDD 4
21 nQ1
IREF 5
20 Q3
Q0
GND ⁶
19 nQ3
MR ⁷
18 BW_SEL1
nQ0
BW_SEL0 8
17 F_SEL1
VDDA ⁹
16 _GND
Q1
F_SEL0 ^{10 15} GND
nQ1
VDD ¹¹
OE ¹²
14 _nCLK
13 _CLK
Q2
ICS871004I-04
nQ2
24-Lead TSSOP
Q3
4.40mm x 7.8mm x 0.92mm
package body
nQ3
G Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT^™ / ICS^™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR
1
ICS871004AGI-04 REV A JANUARY 17, 2008