ICS8705 Datasheet, PDF (9/18 Pages) Integrated Circuit Systems – ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

ICS8705
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
nCLK1
V_OH
CLK1
V_OL
FB_IN
➤ t(Ø)
V_OH
V_DDO
2
V_OL
tjit(Ø) = t(Ø) — t(Ø) mean = Phase Jitter
t(Ø) mean = Static Phase Offset
(where t(Ø) is any random sample, and t(Ø) mean is the average
of the sampled cycles measured on controlled edges)
CLK0
nCLK1
CLK1
Q0:Q7
V_DD
2
V_DDO
2
t➤
PD
PHASE JITTER & STATIC PHASE OFFSET
PROPAGATION DELAY
Q0:Q7
V_DDO
2
t _PW
V_DDO
2
t _PERIOD
odc = ^{t PW}
t _PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
V_DDO
2
8705BY
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9
REV. H JULY 2, 2010