ICS8705 Datasheet, PDF (12/18 Pages) Integrated Circuit Systems – ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR

ICS8705
ZERO DELAY, DIFFERENTIAL-TO-LVCMOS/LVTTL
CLOCK GENERATOR
LAYOUT GUIDELINE
The schematic of the ICS8705 layout example is shown in
Figure 4A. The ICS8705 recommended PCB board layout
for this example is shown in Figure 4B. This layout example is
used as a general guideline. The layout in the actual system will
depend on the selected component types, the density of the
components, the density of the traces, and the stack up of the
P.C. board.
VDD
VDD
R7
10 - 15
C16
10u
VDDA
C11
0.01u
U1
R1 43
Zo = 50
VDD
Ro ~ 7 Ohm
R4 43
Driv er_LVCMOS
VDD=3.3V or 2.5V
Zo = 50
SEL0
SEL1
R5
R4
1K
1K
1
2
3
SEL0
SEL1
4
5
6
7
CLK0
nc
CLK1
nCLK1
8
CLK_SEL
MR
ICS8705
VDDO
Q5
24
23
22
GND
Q4
VDDO
Q3
21
20
19
18
GND
Q2
17
Logic Input Pin Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
R2 43
Zo = 50
(U1-9)
(U1-12)
VDD
(U1-16) (U1-20)
(U1-24)
(U1-28)
(U1-32)
C2
0.1uF
C3
0.1uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C1
0.1uF
C7
0.1uF
FIGURE 4A. ICS8705 LVCMOS CLOCK GENERATOR SCHEMATIC EXAMPLE
8705BY
www.idt.com
12
REV. H JULY 2, 2010