ICS844071 Datasheet, PDF (9/15 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR

ICS844071
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Crystal Input Interface
The ICS844071 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 25MHz, 18pF parallel
resonant crystal and were chosen to minimize the ppm error. The
optimum C1 and C2 values can be slightly adjusted for different
board layouts.
X1
18pF Parallel Crystal
XTAL_IN
C1
33p
XTAL_OUT
C2
22p
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
VDD
Ro
Rs
50Ω
Zo = Ro + Rs
VDD
R1
0.1µf
XTAL_IN
R2
XTAL_OUT
Figure 3. General Disgram for LVCMOS Driver to XTAL Input Interface
IDT™ / ICS™ LVDS CLOCK GENERATOR
9
ICS844071AG SEPTEMBER 26, 2007