ICS844071 Datasheet, PDF (8/15 Pages) Integrated Device Technology – FEMTOCLOCKS™ CRYSTAL-TO-LVDS CLOCK GENERATOR

ICS844071
FEMTOCLOCK™CRYSTAL-TO-LVDS CLOCK GENERATOR
Parameter Measurement Information, continued
V_DD
DC Input LVDS
out
➤
100
V_OD/∆ V_OD
out
Differential Output Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS44071 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V_DD and V_DDA should be individually
connected to the power supply plane through vias, and bypass
capacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10µF and a 0.01µF
bypass capacitor should be connected to each V_DDA pin.
3.3V or 2.5V
VDD
.01µF _10Ω
VDDA
.01µF
10µF
Figure 1. Power Supply Filtering
IDT™ / ICS™ LVDS CLOCK GENERATOR
8
ICS844071AG SEPTEMBER 26, 2007