ICS843S1333D Datasheet, PDF (9/14 Pages) Integrated Device Technology – One differential LVPECL output

ICS843S1333D Data Sheet
CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER
Schematic Example
Figure 5 shows an example of the ICS843S133D application
schematic. In this example, the device is operated at V_CC = 3.3V. The
18pF parallel resonant 20MHz crystal is used. The C1 and C2 = 28pF
are recommended for frequency accuracy. For different board layout,
the C1 and C2 may be slightly adjusted for optimizing frequency
accuracy. Two examples of LVPECL termination are shown in this
schematic. Additional termination approaches are shown in the
LVPECL Termination Application Note.
VCC
R1
10 C4
10uF
VCCA
C5
0.01u
XTAL_OUT
XTAL_IN
U1
1
2
3
4
VCCA
VEE
XTAL_OUT
XTAL_IN
C2
28pF
X1
20MHz
18pF
C1
28pF
Logic Control Input Examples
Set Logic
VCC _{Input to}
'1'
RU1
1K
Set Logic
VCC _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
VCC
VCC
C3
0.01u
VCC
Q
nQ
8
7
6
5
OE
Q
nQ
OE
VCC=3.3V
3.3V
R2
R3
133
133
Zo = 50 Ohm
+
Zo = 50 Ohm
-
R4
R5
82.5
82.5
Zo = 50 Ohm
Zo = 50 Ohm
R6
50
+
-
R7
50
Optional
R8
Y-Termination
50
Figure 5. ICS843S1333D Schematic Example
ICS843S1333DG REVISION A MAY 6, 2010
9
©2010 Integrated Device Technology, Inc.