ICS843S1333D Datasheet, PDF (6/14 Pages) Integrated Device Technology – One differential LVPECL output

ICS843S1333D Data Sheet
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter performance,
power supply isolation is required. The ICS843S1333D provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V_CC and V_CCA should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V_CC pin and also shows that V_CCA requires that an
additional 10Ω resistor along with a 10µF bypass capacitor be
connected to the V_CCA pin.
CRYSTAL-TO-3.3V LVPECL CLOCK SYNTHESIZER
3.3V
V_CC
.01µF _10Ω
V_CCA
.01µF
10µF
Figure 1. Power Supply Filtering
Crystal Input Interface
The ICS843S1333D has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in Figure
2 below were determined using a 20MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error. The optimum C1
and C2 values can be slightly adjusted for different board layouts.
External tuning capacitor must be used for proper operation.
X1
18pF Parallel Crystal
C1
28pF
XTAL_IN
C2
28pF
XTAL_OUT
Figure 2. Crystal Input Interface
ICS843S1333DG REVISION A MAY 6, 2010
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