9ZXL1231 Datasheet, PDF (9/18 Pages) Integrated Device Technology – Space-saving 64 VFQFPN package

9ZXL1231 DATASHEET
Electrical Characteristics–Skew and Differential Jitter Parameters
T_AMB = T_COM or T_IND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0]
t_{SPO_PLL}
Input-to-Output Skew in PLL mode
@ nominal temperature and voltage
-100 -60 100
ps 1,2,4,5,8
CLK_IN, DIF[x:0]
t_{PD_BYP}
Input-to-Output Skew in Bypass mode
@ nominal temperature and voltage
2.5 3.6 4.5
ns 1,2,3,5,8
CLK_IN, DIF[x:0]
t_{DSPO_PLL}
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
-50
0
50
ps 1,2,3,5,8
CLK_IN, DIF[x:0]
t_{DSPO_BYP}
Input-to-Output Skew Varation in Bypass mode
T_AMB = T_COM
Input-to-Output Skew Varation in Bypass mode
T_AMB = T_IND
-250
-350
250
ps 1,2,3,5,8
350
ps 1,2,3,5,8
DIF{x:0]
t_{SKEW_ALL}
Output-to-Output Skew across all outputs
@100MHz, T_AMB = T_COM
Output-to-Output Skew across all outputs @
100MHz, T_AMB = T_IND
30 50
ps
1,2,3,8
30 65
ps
1,2,3,8
PLL Jitter Peaking
j_peak-hibw
LOBW#_BYPASS_HIBW = 1
0 1.2 2.5
dB
7,8
PLL Jitter Peaking
j_peak-lobw
LOBW#_BYPASS_HIBW = 0
0 0.8 2
dB
7,8
PLL Bandwidth
PLL Bandwidth
pll_HIBW
pll_LOBW
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
2
3
4
MHz
8,9
0.7 1.1 1.4 MHz
8,9
Duty Cycle
t_DC
Duty Cycle Distortion
t_DCD
Measured differentially, PLL Mode
45 50 55
%
1
Measured differentially, Bypass Mode
-1.5 -0.6 0
%
1,10
@100MHz
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
34 50
ps
1,11
1
5
ps
1,11
Notes for preceding table:
1 _{Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.}
2 _{Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.}
3 _{All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.}
4 _{This parameter is deterministic for a given device}
5 _{Measured with scope averaging on to find mean value.}
6._{t is the period of the input clock}
7 _{Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.}
8. _{Guaranteed by design and characterization, not 100% tested in production.}
9 _{Measured at 3 db down or half power point.}
10 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mod}
11 _{Measured from differential waveform}
REVISION F 07/14/15
9
DB1200ZL 12-OUTPUT LOW POWER HCSL BUFFER