9ZXL1231 Datasheet, PDF (17/18 Pages) Integrated Device Technology – Space-saving 64 VFQFPN package

9ZXL1231 DATASHEET
Revision History
Rev.
A
B
C
D
E
F
Issuer
RDW
RDW
RDW
RDW
RDW
RDW
Issue Date
4/14/2011
8/3/2011
12/8/2011
4/9/2012
5/11/2012
7/14/2015
Description
Page #
1. Updated Byte 0, PD# current and OE# Latency specs.
2. Updated electrical tables with Characterization Data. Move to Final
3. Corrected Pin Description, pin 37 was missing
4. Corrected Pin 5 in pinout. Name was truncated.
1. Functionality added to Byte 0 [3:1]. Byte 0, bit 3 enables SW control of
PLL BW and Bypass mode. Byte 0[2:1] is read write to mimic the
readback status of Byte 0[7:6]. See SMBus table.
1. Changed Output Features description
2. Fixed alignment issue in Power Connections Table - cosmetic fix, table
information was and is correct.
3. Updated tDSPO_BYP to +/-250ps
4. Updated Differential Test Loads Figure to indicate impedance and trace
length.
5. Removed SMBus Address info on page 12, SMBus address is
selectable as indicated on page 3.
6. Idd revised downward in Current Consumption Table
1. Corrected Power Connections table, first column, last row. VDD for DIF
clocks are pins 24, 40 and 57.
1. Minor updates to some typical values in electrical tables, missing
typical values added.
2. DS title changed from "12-Output Low Power Differential Buffer for PCIe
Gen3 and QPI" to "12-Output Low Power Differential Buffer for PCIe
Gen1/2/3 and QPI" to emphasize backwards compatibility.
3. Added comment to Vswing parameter on input clock to denote that the
value is a single-ended value.
4. Max IDDIO chanded from 106mA to 110mA.
1. Updated front page text
2. Updated electrical tables with information for Industrial Temp device,
where needed
3. Updated electrical tables to latest format.
4. Revised DIF_IN specification to match PCI SIG input requirements
5. Added Industrial Temp ordering information.
1,2,8,9,11,
12
2
Various
Various
REVISION F 07/14/15
17
DB1200ZL 12-OUTPUT LOW POWER HCSL BUFFER