9DBV0641_16 Datasheet, PDF (9/17 Pages) Integrated Device Technology – 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB

9DBV0641 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = T_AMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
PLL Bandwidth
PLL Jitter Peaking
Duty Cycle
BW
t_JPEAK
t_DC
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
Measured differentially, PLL Mode
1.8
2.7
3.8
0.8
1.4
2
1.3
2
45
50.1
55
UNITS
MHz
MHz
dB
%
NOTES
1,5
1,5
1
1
Duty Cycle Distortion
t_DCD Measured differentially, Bypass Mode @100MHz -1
0
1
%
1,3
Skew, Input to Output
t_pdBYP
t_pdPLL
Bypass Mode, V_T = 50%
PLL Mode V_T = 50%
3000
3600
4500
ps
1
0
-4
200
ps
1,4
Skew, Output to Output
t_sk3
V_T = 50%
39
50
ps
1,4
Jitter, Cycle to cycle
t_jcyc-cyc
PLL mode
Additive Jitter in Bypass Mode
14
50
0.1
5
ps
1,2
ps
1,2
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Measured from differential waveform}
3 _{Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.}
4 _{All outputs at default slew rate}
5 _{The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.}
Electrical Characteristics–Phase Jitter Parameters
TA = T_AMB; Supply Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Phase Jitter, PLL Mode
SYMBOL
t_jphPCIeG1
t_jphPCIeG2
t_jphPCIeG3
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3 Common Clock Architecture
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
t_jphPCIeG3SRn PCIe Gen 3 Separate Reference No Spread (SRnS)
S
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
MIN
TYP
31
0.8
2.3
0.5
0.5
MAX
52
1.4
2.5
0.6
0.6
INDUSTRY
LIMIT UNITS Notes
86 ps (p-p) 1,2,3,5
3
ps
(rms)
1,2,3,5
3.1
ps _1,2,3,5
(rms)
1
ps _1,2,3,5
(rms)
0.7
ps _1,2,3,5
(rms)
Additive Phase Jitter
t_jphSGMII
125MHz, 1.5MHz to 20MHz, -20dB/decade
rollover < 1.5MHz, -40db/decade rolloff > 10MHz
t_jphPCIeG1
PCIe Gen 1
t_jphPCIeG2
t_jphPCIeG3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
125MHz, 1.5MHz to 10MHz, -20dB/decade
t_{jphSGMIIM0 rollover < 1.5MHz, -40db/decade rolloff > 10MHz}
1.9
2
0.1
5
0.1
0.4
0.01
0.4
0.00
0.1
165
200
N/A
ps _1,2,3,5
(rms)
N/A
ps
1,2,3
(p-p)
N/A
ps
(rms)
1,2,5
N/A
ps
1,2,5
(rms)
N/A
ps _1,2,4,5
(rms)
N/A
fs
(rms)
1,6
t_jphSGMIIM1
125MHz, 12kHz to 20MHz, -20dB/decade rollover
< 1.5MHz, -40db/decade rolloff > 10MHz
251
300
N/A
fs
1,6
(rms)
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]}
5 _{Driven by 9FGV0831 or equivalent}
6 _{Rohde&Schartz SMA100}
REVISION D 04/28/16
9
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS