9DBV0641_16 Datasheet, PDF (2/17 Pages) Integrated Device Technology – 6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB

9DBV0641 DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSADR_tri 1
30 NC
^vHIBW_BYPM_LOBW# 2
29 vOE3#
FB_DNC 3
28 DIF3#
FB_DNC# 4
VDDR1.8 5
9DBV0641
27 DIF3
26 VDDIO
CLK_IN 6
CLK_IN# 7
Paddle is GND
25 VDDA1.8
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
40-pin VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
5mm x 5mm 0.4mm pin pitch
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+ Read/Write bit
x
x
x
Power Management Table
CKPWRGD_PD#
CLK_IN
SMBus
OEx bit
OEx# Pin
DIFx
True O/P Comp. O/P
PLL
0
X
X
X
Low
Low
Off
1
Running
0
X
Low
Low
On¹
1
Running
1
0
Running Running
On¹
1
Running
1
1
Low
Low
On¹
1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table.
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
2
REVISION D 04/28/16