9DBL0641 Datasheet, PDF (9/19 Pages) Integrated Device Technology – 6-output 3.3V PCIe Zero-Delay Buffer

9DBL0641 / 9DBL0651 DATASHEET
ERleefcetrreicnacleCInhdaerapcetnedriesntitcSs–pFreilatedre(SdRPISh)asAercJhititteerctPuarreasm₅ eters - PCIe Separate
T_AMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX ^INDUSTRY UNITS Notes
LIMIT
Phase Jitter, PLL Mode
t_jphPCIeG2-
SRIS
t_jphPCIeG3-
SRIS
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
1.2
1.5
n/a
2
ps
1,2
(rms)
0.5
ps
(rms) ^1,2,6
Additive Phase Jitter,
Bypass mode
1 _{Applies to all outputs.}
t_jphPCIeG2-
SRIS
t_jphPCIeG3-
SRIS
PCIe Gen 2
(PLL BW of 16MHz , CDR = 5MHz)
PCIe Gen 3
(PLL BW of 2-4MHz or 2-5MHz, CDR = 10MHz)
0.0
0.01
0.0
0.01
ps
1,2,4
(rms)
n/a
ps
(rms) ^1,2,4,6
2 _{Based on PCIe Base Specification Rev3.1a. These filters are different than Common Clock filters. See http://www.pcisig.com for latest specifications.}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter.}
5 _{As of PCIe Base Specification Rev4.0 draft 0.7, SRIS is not currently defined for Gen1 or Gen4.}
6 _{This device does not support PCIe Gen3 SRIS in PLL mode. It supports PCIe Gen3 SRIS in bypass mode.}
Electrical Characteristics– Unfiltered Phase Jitter Parameters
TA = T_AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
INDUSTRY
MAX
LIMIT UNITS Notes
156.25MHz, 1.5MHz to 10MHz, -20dB/decade
Additive Phase Jitter,
t_{jph156M rollover < 1.5MHz, -40db/decade rolloff > 10MHz}
159
N/A
Fanout Mode
t_jph156M12k- 156.25MHz, 12kHz to 20MHz, -20dB/decade
20
rollover <12kHz, -40db/decade rolloff > 20MHz
363
N/A
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{DRiven by Rohde&Schartz SMA100}
3 _{For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]}
fs
(rms)
fs
(rms)
1,2,3
1,2,3
FEBRUARY 8, 2017
9
6-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER