9DB106 Datasheet, PDF (9/14 Pages) Integrated Device Technology – Six Output Differential Buffer for PCIe Gen 2

9DB106
Six Output Differential Buffer for PCIe Gen 2
General SMBus serial interface information for the 9DB106
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D4 _(h)
• IDT clock will acknowledge
• Controller (host) sends the begining byte location = N
• IDT clock will acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1)
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D4 _(h)
• IDT clock will acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D5 _(h)
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N + X -1
• IDT clock sends Byte 0 through byte X (if X_(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
starT bit
IDT (Slave/Receiver)
Slave Address D4_(h)
WR
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P
stoP bit
ACK
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
T
starT bit
Slave Address D4_(h)
WR
WRite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D5_(h)
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
IDT^® Six Output Differential Buffer for PCIe Gen 2
N Not acknowledge
P
stoP bit
Byte N + X - 1
9DB106 REV K 04/20/11
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