9DB106 Datasheet, PDF (5/14 Pages) Integrated Device Technology – Six Output Differential Buffer for PCIe Gen 2

9DB106
Six Output Differential Buffer for PCIe Gen 2
Electrical Characteristics - Clock Input Parameters
TA = T_COM or T_IND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage -
DIF_IN
Input Low Voltage -
DIF_IN
Input Common Mode
Voltage - DIF_IN
V_IHDIF
V_ILDIF
V_COM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
MIN
600
V_SS - 300
300
Input Amplitude - DIF_IN V_SWING
Peak to Peak value
300
Input Slew Rate - DIF_IN dv/dt
Measured differentially
0.4
Input Leakage Current
I_IN
V_IN = V_{DD ,} V_IN = GND
-5
Input Duty Cycle
d_tin
Measurement from differential
45
wavefrom
Input Jitter - Cycle to
Cycle
J_DIFIn
Differential Measurement
0
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2_{Slew rate measured through +/-75mV window centered around differential zero}
TYP
800
0
MAX
1150
UNITS NOTES
mV
1
300
mV
1
1000
mV
1
1450
mV
1
8
V/ns 1,2
5
uA
1
55
%
1
125
ps
1
Electrical Characteristics - PLL Parameters
TA = T_COM or T_IND; Supply Voltage VDD = 3.3 V +/-5%
Group
Parameter
Description
PLL Jitter Peaking j_peak-hibw
(PLL_BW = 1)
Min Typ Max Units Notes
0
1 2.5 dB
1,4
PLL Jitter Peaking j_peak-lobw
(PLL_BW = 0)
0
1
2
dB
PLL Bandwidth
pll_HIBW
(PLL_BW = 1)
PLL Bandwidth
pll_LOBW
(PLL_BW = 0)
PCIe Gen 1 phase jitter
(1.5 - 22 MHz)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
Jitter, Phase
t_jphasePLL
(PLL_BW=1)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Hi-Band >1.5MHz
(PLL_BW=0)
PCIe Gen 2 jitter
(8-16 MHz, 5-16 MHz) Lo-Band <1.5MHz
NOTES:
1. Guaranteed by design and characterization, not 100% tested in production.
2. See http://www.pcisig.com for complete specs
2 2.5
0.4 0.5
3 MHz
1 MHz
40 108 ps
2.7 3.1 ps rms
2.2 3.1 ps rms
1.3 3 ps rms
3. Device driven by 932S421BGLF or equivalent
4. Measured as maximum pass band gain. At frequencies w ithin the loop BW, highest point of magnification is called PLL jitter peaking.
5. Measured at 3 db dow n or half pow er point.
1,4
1,5
1,5
1,2,3
1,2,3
1,2,3
1,2,3
IDT^® Six Output Differential Buffer for PCIe Gen 2
9DB106 REV K 04/20/11
5