8T49N488 Datasheet, PDF (9/36 Pages) Integrated Device Technology – Fourth generation FemtoClock

8T49N488 DATA SHEET
If operating in Low Bandwidth Frequency Translation mode, the PLL
will continue to reference itself to the local reference and will hold its
output phase and frequency in relation to that source. Output stability
is determined by the stability of the local reference REFCLK in this
case.
However, if operating in High Bandwidth Frequency Translation
mode, the PLL no longer has any frequency reference to use and out-
put stability is now determined by the stability of the internal VCO.
If the device is programmed to perform Manual switching, once the
selected input reference recovers, the 8T49N488 will switch back to
that input reference. If programmed for either Automatic mode, the
device will switch back to whichever input reference has a valid clock
first.
Output Configuration
The two outputs of each PLL both provide the same clock frequency.
The two outputs are individually selectable as LVDS or LVPECL out-
put types via the Q0_TYPE and Q1_TYPE register bits. when the
output is disabled, it will show a high impedance condition.
Serial Interface Configuration Description
The 8T49N488 has an I²C-compatible configuration interface to ac-
cess any of the internal registers (Table 4D) for frequency and PLL
parameter programming. Each PLL acts as a slave device on the I²C
bus and has the address 0b11011xx, where xx is set to fixed value by
A0 & A1 (see Table 4A for details). The interface accepts byte-orient-
ed block write and block read operations. An address byte (P) speci-
fies the register address (Table 4D) as the byte position of the first
register to write or read. Data bytes (registers) are accessed in se-
quential order from the lowest to the highest byte (most significant bit
first, see table 4B, 4C). Read and write block transfers can be stop-
ped after any complete byte transfer. It is recommended to terminate
I²C the read or write transfer after accessing byte #23 of each PLL.
For full electrical I²C compliance, it is recommended to use external
pull-up resistors for SDATA and SCLK.
Note: If a different device slave address is desired, please contact
IDT.
Table 4A. I²C Device Slave Address
A6
A5
A4
A3
A2
A1
A0
R/W
PLL-A
1
1
0
1
1
0
0
R/W
PLL-B
1
1
0
1
1
0
1
R/W
PLL-C
1
1
0
1
1
1
0
R/W
PLL-D
1
1
0
1
1
1
1
R/W
Table 4B. Block Write Operation
Bit
1
2:8
9
10 11:18 19 20:27 28 29-36 37
...
...
...
Description
Slave
START Address
W (0)
ACK
Address
Byte (P)
Data Byte
Data Byte
ACK
(P)
ACK
(P+1)
ACK
Data Byte
...
ACK
STOP
Length (bits)
1
7
1
1
8
1
8
1
8
1
8
1
1
Table 4C. Block Read Operation
Bit
1
2:8
9 10 11:18 19 20
21:27 28 29 30:37 38 39-46 47
Description
START
Slave
Address
W
(0)
A
C
K
Address
Byte (P)
A
C
K
Repeate Slave R
d START Address (1)
A
C
K
Data
Byte (P)
A
C
K
Data
Byte
(P+1)
A
C
K
Length (bits)
1
7
1
1
8
1
1
7
1
1
8
1
8
1
...
Data
Byte
...
8
... ...
A
C STOP
K
1
1
REVISION B 03/23/15
9
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