8T49N488 Datasheet, PDF (1/36 Pages) Integrated Device Technology – Fourth generation FemtoClock

FemtoClock^® NG QUAD Universal
Frequency Translator
8T49N488
DATA SHEET
General Description
The 8T49N488 is a quad PLL with FemtoClock^® NG technology, it
integrates low phase noise Frequency Translator / Synthesizer, Jitter
attenuation, and with alarm and monitoring functions suitable for
networking and communications applications. The device has four
fully independent PLLs, each PLL is able to generate any output
frequency in the 0.98MHz - 312.5MHz range and most output
frequencies in the 312.5MHz - 1,300MHz range (see Table 3 for
details). A wide range of input reference clocks and operation
reference clock may be used as the source for the output frequency.
Each PLL of 8T49N488 has three operating modes to support a very
broad spectrum of applications:
1) Frequency Synthesizer
• Synthesizes output frequencies from an external reference
clock REFCLK.
• Fractional feedback division is used, so there are no
requirements for any specific input reference clock frequency to
produce the desired output frequency with a high degree of
accuracy.
2) High-Bandwidth Frequency Translator
• Applications: PCI Express, Computing, General Purpose
• Translates any input clock in the 16MHz - 710MHz frequency
range into any supported output frequency.
• This mode has a high PLL loop bandwidth in order to track input
reference changes, such as Spread-Spectrum Clock
modulation.
3) Low-Bandwidth Frequency Translator
• Applications: Networking & Communications.
• Translates any input clock in the 8kHz -710MHz frequency
range into any supported output frequency.
• This mode supports PLL loop bandwidths in the 10Hz - 580Hz
range and makes use of an external REFCLK to provide
significant jitter attenuation.
Each PLL provides factory-programmed default power-up
configuration burned into One-Time Programmable (OTP) memory.
The configuration is specified by customer and are programmed by
IDT during the final test phase from an on-hand stock of blank
devices.
To implement other configurations, these power-up default settings
can be overwritten after power-up using the I²C interface and the
device can be completely reconfigured.
Features
• Fourth generation FemtoClock^® NG technology
• Four fully independent PLLs
• Universal Frequency Translator^TM/Frequency Synthesizer and
Jitter attenuator
• Outputs are programmable as LVPECL or LVDS
• Programmable output frequency: 0.98MHz up to 1,300MHz
• Two differential inputs support the following input levels:
LVPECL, LVDS, LVHSTL, HCSL
• Input frequency range: 8kHz ~ 710MHz Low-Bandwidth
• Input frequency range: 16MHz ~ 710MHz High-Bandwidth
• REFCLK frequency range: 16MHz ~ 40MHz
• Input clock monitor and alarm
• Smoothed reference switch
• Factory-set register configuration for power-up default state
• Power-up default configuration
• Configuration customized via One-Time Programmable ROM
• Settings may be overwritten after power-up via I²C
• I²C Serial interface for register programming
• RMS phase jitter at 161.1328125MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 465fs (typical), Low Bandwidth Mode (FracN)
• RMS phase jitter at 400MHz,using 40MHz REFCLK
(12kHz ~ 20MHz): 333fs (typical), Synthesizer Mode (Integer FB)
• Full 2.5V ±5% supply mode
• -40°C to 85°C ambient operating temperature
• 10mm X 10mm CABGA package
• Lead-free (RoHS 6) packaging
8T49N488 REVISION B 03/23/15
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