89HPES24NT24G2 Datasheet, PDF (9/35 Pages) Integrated Device Technology – Supports 128 Bytes to 2 KB maximum payload size

IDT 89HPES24NT24G2 Datasheet
Signal
GPIO[6]
GPIO[7]
GPIO[8]
Type
Name/Description
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: FAILOVER1
1st Alternate function pin type: Input
1st Alternate function: When this signal changes state and the correspond-
ing failover capability is enabled, a failover event is signaled.
2nd Alternate function pin name: FAILOVER3
2nd Alternate function pin type: Input
2nd Alternate function: When this signal changes state and the correspond-
ing failover capability is enabled, a failover event is signaled.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: FAILOVER2
1st Alternate function pin type: Input
1st Alternate function: When this signal changes state and the correspond-
ing failover capability is enabled, a failover event is signaled.
2nd Alternate function pin name: P8LINKUPN
2nd Alternate function pin type: Output
2nd Alternate function: Port 8 Link Up Status output.
I/O General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
1st Alternate function pin name: IOEXPINTN
1st Alternate function pin type: Input
1st Alternate function: IO expander interrupt.
2nd Alternate function pin name: P8ACTIVEN
2nd Alternate function pin type: Output
2nd Alternate function: Port 8 Link Active Status Output.
Table 5 General Purpose I/O Pins (Part 2 of 2)
Signal
STK2CFG[4:0]
STK3CFG[4:0]
Type
Name/Description
I Stack 2 Configuration. These pins select the configuration of stack 2.
I Stack 3 Configuration. These pins select the configuration of stack 3.
Table 6 Stack Configuration Pins
Signal
CLKMODE[1:0]
GCLKFSEL
Type
Name/Description
I Clock Mode. These signals determine the port clocking mode used by ports of the
device.
I Global Clock Frequency Select. These signals select the frequency of the GCLKP
and GCLKN signals.
0x0 100 MHz
0x1 125 MHz
Table 7 System Pins (Part 1 of 2)
9 of 35
December 17, 2013