84321I Datasheet, PDF (9/18 Pages) Integrated Device Technology – 260MHz, Crystal-to-3.3V Differential

84321I DATA SHEET
APPLICATION INFORMATION
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
CRYSTAL INPUT INTERFACE
The 84321I has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 3 below were
determined using a 25MHz, 18pF parallel resonant crystal and
were chosen to minimize the ppm error. These same capacitor
values will tune any 18pF parallel resonant crystal over the
frequency range of 14MHz to 40MHz providing the other param-
eters specified in Table 6, Crystal Characteristics, are satisfied.
REVISION B 11/5/15
X1
18pF Parallel Cry stal
XTAL2
C1
18p
XTAL1
C2
22p
84321
FIGURE 3. CRYSTAL INPUt INTERFACE
9
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER