84321I Datasheet, PDF (10/18 Pages) Integrated Device Technology – 260MHz, Crystal-to-3.3V Differential

84321I DATA SHEET
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply
pins are vulnerable to random noise. The 84321I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V_CC, V_CCA, and
V_CCO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 4 illustrates how
a 24Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each V_CCA pin.
V_CC
V_CCA
3.3V
.01μF
24Ω
.01μF
10 μF
FIGURE 4. POWER SUPPLY FILTERING
LAYOUT GUIDELINE
The schematic of the 84321I layout example used in this layout
guideline is shown in Figure 5A. The 84321I recommended
PCB board layout for this example is shown in Figure 5B. This
layout example is used as a general guideline. The layout in the
actual system will depend on the selected component types,
the density of the components, the density of the traces, and
the stack up of the P.C. board.
U1
1
2
3
4
5
6
7
8
M5
M6
M7
M8
N0
N1
nc
VEE
ICS84321
C14
0.1u
C1
C2
X1
VCC
XTAL2
T_CLK
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
24
23
22
21
20
19
18
17
REF_IN
XTAL_SEL
S_LOAD
S_DATA
S_CLOCK
VCCA
C11
0.01u
R7
24
C16
10u
C15
0.1u
Zo = 50 Ohm
IN+
TL1
Zo = 50 Ohm
IN-
TL2
VCC
R1
R3
125
125
+
-
R2
R4
84
84
260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECL FREQUENCY SYNTHESIZER
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT
10
REVISION B 11/5/15